Dynamic ram device having high read operation speed

ABSTRACT

In a dynamic random access memory device including a plurality of word lines, a plurality of bit lines, and a plurality of dynamic memory cells connected to the word lines and the bit lines, a switching circuit is provided between one pair of the bit lines and one sense amplifier, and a switching amplifier is provided between one pair of the bit lines and a read amplifier. Before the connection of the sense amplifier by the switching circuit to the pair of the bit lines, the read amplifier is connected by the switching amplifier to the pair of the bit lines.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a dynamic random access memory (DRAM)device, and more particularly, to an improvement of the read operationspeed of the DRAM.

2. Description of the Related Art

The capacity of semiconductor memory devices has been largely developed.In the past years, the capacity of semiconductor memory devices hasincreased about four times every three years. At present, 256 Mbit DRAMdevices have been disclosed at scientific societies and the like, andsamples of 64 Mbit DRAM devices have appeared on the market. Since onememory cell of a DRAM device is constructed by two elements, i.e., onemetal oxide semiconductor (MOS) transistor and one capacitor, the DRAMdevices are advantageous in respect to the integration as compared withstatic random access memory (SRAM) devices whose memory cell isconstructed by six elements. The DRAM devices of one generation havefour times the capacity of SRAM devices of the same generation. That is,there is a large difference in capacity between the DRAM devices and theSRAM devices.

On the other hand, the SRAM devices have an advantage in that operationspeed is very high. For example, the operation speed time of a 16 MbitDRAM device is about 60 ns due to its synchronous operation, while thatof a 4 Mbit SRAM device is about 20 ns due to its asynchronousoperation. However, the asynchronous operation of DRAM devices is notessential. Actually, some DRAM devices can be operated asynchronously ina special mode such as a static column operation mode, and in this case,the operation speed is about 20 ns, the same as in the SRAM devices.

The low operation speed of the DRAM devices is due to the read operationthereof. That is, in a prior art DRAM device including a plurality ofword lines, a plurality of bit lines and a plurality of dynamic memorycells connected to the word lines and the bit lines, one pair of the bitlines are connected to one sense amplifier which is connected by aswitching circuit to a read amplifier. Therefore, after the senseamplifier is operated to enter a refresh mode, the read amplifier isconnected by the switching circuit to the read amplifier to enter a readmode. As a result, the read operation speed is reduced. This will beexplained later in detail.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a high readoperation speed DRAM device.

According to the present invention, in a DRAM device including aplurality of word lines, a plurality of bit lines and a plurality ofdynamic memory cells connected to the word lines and the bit lines, aswitching circuit is provided between one pair of the bit lines and onesense amplifier, and a switching amplifier is provided between one pairof the bit lines and a read amplifier. Before the connection of thesense amplifier by the switching circuit to the pair of the bit lines,the read amplifier is connected by the switching amplifier to the pairof the bit lines. That is, before entering a refresh mode, the controlenters a read mode.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be more clearly understood from thedescription as set forth below, as compared with the prior art, withreference to the accompanying drawings, wherein:

FIG. 1 is a circuit diagram illustrating a prior art DRAM device;

FIG. 2 is a detailed circuit diagram of the sense amplifier of FIG. 1;

FIG. 3A is a detailed circuit diagram of the read amplifier of FIG. 1;

FIG. 3B is a detailed circuit diagram of the write amplifier of FIG. 1;

FIG. 4 is a timing diagram showing the operation of the device of FIG.1;

FIG. 5 is a circuit diagram illustrating one memory cell of a prior artSRAM device;

FIG. 6 is a circuit diagram illustrating a first embodiment of the DRAMdevice according to the present invention;

FIG. 7 is a detailed circuit diagram of the read amplifier of FIG. 6;

FIG. 8 is a timing diagram showing the operation of the device of FIG.6;

FIG. 9 is a circuit diagram illustrating a second embodiment of the DRAMdevice according to the present invention;

FIG. 10 is a timing diagram showing the operation of the device of FIG.9; and

FIG. 11 is a circuit diagram illustrating a third embodiment of the DRAMdevice according to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Before the description of the preferred embodiments, a prior art DRAMdevice will be explained with reference to FIGS. 1, 2 and 3.

In FIG. 1, which is a circuit diagram illustrating a prior art DRAMdevice, memory cells C₁₁, . . . , C₂₁, . . . are provided at staggeredintersections of word lines WL₁, WL₂, . . . and bit lines BL₁, BL₁ , . .. One pair of the bit lines, such as BL₁ and BL₁ , are connected to onesense amplifier SA₁ having a refresh function or a rewriting function.Also, the bit lines, such as BL₁ and BL₁ , are connected by columnselection transistors Q₁ and Q₂ to input/output lines I/O and I/O. Thecolumn selection transistors Q₁ and Q₂ are controlled by a Y selectionsignal φ_(Y1). Therefore, one pair of the bit lines are selected by Yaddress signals, and are connected to the input/output lines I/O andI/O. The input/output lines I/O and I/O are connected to a readamplifier RA and a write amplifier WA.

As illustrated in FIG. 2, the sense amplifier SA₁ is constructed by aflip-flop formed by P-channel transistors Q_(P1) and Q_(P2) connected toa driving line φ_(SP) and N-channel transistors Q_(N1) and Q_(N2)connected to a driving line φ_(SN). When a P-channel transistor Q_(SP)is turned ON by a sense activation signal φ_(S), the high voltage lineφ_(SP) is made V_(cc). On the other hand, when an N-channel transistorQ_(SN) is turned ON by a sense activation signal φ_(S), the high voltageline φ_(SN) is made GND. Information is stored as a charge in acapacitor of a memory cell such as C₁₁. In a read mode, the chargestored in the capacitor C₁₁ is divided between the capacity of thecapacitor C₁₁ and a parasitic capacity of a bit line BL₁, and as aresult, a difference in potential is generated between the bit lines BL₁and BL₁ . In this case, although a capacitance ratio of the bit line BL₁to the memory cell C₁₁ is very large, this difference in potential isless than 100 mV. Also, the charge stored in the memory cell C₁₁ isalmost discharged to the bit line BL₁, and therefore, the informationstored in the memory cell C₁₁ is almost destroyed. In order to amplifythe signals on the bit lines and remedy or refresh the informationstored in the memory cells, the sense amplifier, such as SA₁, isconnected to the bit lines BL₁ and BL₁ .

As illustrated in FIG. 3A, the read amplifier RA has a similarconfiguration to the sense amplifier SA₁. That is, the read amplifier RAis constructed by P-channel transistors Q_(P3), Q_(P4) and Q_(P5)corresponding to the transistors Q_(P1), Q_(P2) and Q_(SP),respectively, of FIG. 2 and N-channel transistors Q_(N3), Q_(N4) andQ_(N5) corresponding to the transistors Q_(N1), Q_(N2) and Q_(SN),respectively, of FIG. 2. Thus, the read amplifier RA is controlled byread signals φ_(R) and φ_(R) to amplify the difference in potentialbetween the input/output lines I/O and I/O, to thereby generate outputdata signals D_(OUT) and D_(OUT).

Also, as illustrated in FIG. 3B, the write amplifier WA is constructedby an inverter formed by P-channel transistors Q_(P6) and Q_(P7) andN-channel transistors Q_(N6) and Q_(N7). Thus, the write amplifier WAforcibly changes voltages at the input/output lines I/O and I/O inaccordance with input data signals D_(IN) and D_(IN).

A read operation upon the device of FIG. 1 is explained next withreference to FIG. 4. Assume that the bit lines BL₁ and BL₁ and theinput/output lines I/O and I/O are precharged at V_(cc) /2 by aprecharging circuit (not shown).

At time t₀, an external row address strobe signal RAS is made low toenter a selection mode. As a result, a control circuit (not shown) isoperated to operate an X-address buffer/decoder (not shown). Thus, attime t₁, the voltage at a selected word line such as WL₁ is made higherthan V_(cc).

When the voltage at the word line WL₁ is made higher, the transistor ofthe memory cell C₁₁ is completely turned ON. As a result, the charge atthe node N₁₁ is divided between the the capacitor of the memory cell C₁₁and the bit line BL₁, and therefore, a difference ΔV in potential isgenerated between the bit lines BL₁ and BL₁ . In this case, since acapacitance ratio of the bit line BL₁ to the capacitor of the memorycell C₁₁ is very large, this difference is very small, for example,about 100 mV.

At time t₂, the transistors Q_(SP) and Q_(SN) of the sense amplifier SA₁are turned ON by the sense activation signals φ_(S) and φ_(S), so thatthe control enters a refresh mode. That is, the sense amplifier SA₁ isactivated by causing the voltage lines φ_(SP) and φ_(SN) to be V_(cc)and 0 V (GND), respectively. As a result, the voltage at the bit lineBL₁ on a lower voltage side becomes 0 V, and the voltage at the bit lineBL₁ becomes V_(cc), thus carrying out a sense operation as well as arefresh operation.

At time t₃, when the sense operation and the refresh operation have beencarried out, the transistors Q₁ and Q₂ are turned ON by the Y selectionsignal φ_(Y1), so that the signals at the bit lines BL₁ and BL₁ aretransferred to the input/output lines I/O and I/O, respectively. In thiscase, the transfer of the signals from the bit lines bit lines BL₁ andBL₁ is initially carried out in accordance with a capacitance ratio ofthe bit lines BL₁ and BL₁ to the input/output lines I/O and I/O. Thatis, in an initial state, the amounts of the signals at the bit lines BL₁and BL₁ are reduced. Then, the read amplifier RA initiates an amplifyingoperation upon the input/output lines I/O and I/O by the read signalsφ_(R) and φ_(R). Finally, the voltages at the bit lines BL₁ and BL₁ aswell as the voltages at the input/output lines I/O and I/O are amplifiedto V_(cc) and GND.

Then, at time t₄, the control returns to a stand-by mode.

On the other hand, as illustrated in FIG. 5, a memory cell of a SRAMdevice is constructed by a flip-flop formed by P-channel transistorsQ_(P8) and Q_(P9) and N-channel transistors Q_(N8) and Q_(N9), andtransfer gates Q_(N10) and Q_(N11). The transfer gates Q_(N10) andQ_(N11) are controlled by a voltage at a word line WL, to therebyconnect cell nodes to bit lines BL and BL. That is, in the senseamplifier SA₁ of FIG. 2, when the high voltage line φ_(SP) and the lowvoltage line φ_(SN) are fixed at V_(cc) and GND, respectively, the senseamplifier SA₁ of FIG. 2 serves as the memory cell of the SRAM device.Therefore, the memory cell of the SRAM device per se has anamplification function, and therefore, can output larger or higherlevels of signals to the bit lines BL and BL. Thus, the SRAM device doesnot require a refresh operation and sense amplifiers as in the DRAMdevice. In other words, in the SRAM device, since an sense amplifier isincluded in each of the memory cells, signals are transmitted to theinput/output lines without waiting for the operation of the senseamplifiers. Thus, the read operation speed of the SRAM device is higherthan that of the DRAM device.

In FIG. 6, which illustrates a first embodiment of the presentinvention, the input/output lines I/O and I/O of FIG. 1 are divided intoread bus lines RB and RB and write bus lines WB and WB. In other words,the input/output lines I/O and I/O of FIG. 1 correspond to the write buslines WB and WB specifically for a write operation, and the read buslines RB and RB are added specifically for a read operation.

A connection between the bit lines BL₁ and BL₁ and the read bus lines RBand RB is carried out not by a direct coupling such as a drain-sourcecoupling of transistors such as Q₁ and Q₂, but by a capacitive coupling.That is, an amplifier AMP is interposed between the bit lines BL₁ andBL₁ and the read bus lines RB and RB. The amplifier AMP is constructedby P-channel transistors Q₃ and Q₄ and N-channel transistors Q₅ and Q₆.The bit lines BL₁ and BL₁ are connected to gates of the transistors Q₃and Q₄, respectively, and the read lines RB and RB are connected todrains of the transistors Q₃ and Q₄. Therefore, since gate insulatinglayers of the transistors Q₃ and Q₄ are interposed between the bit linesBL₁ and BL₁ and the read bus lines RB and RB, no current flowtherethrough. Also, although the levels of signals to be transmitted arereduced in accordance with the gate capacities of the gate insulatinglayers of the transistors Q₃ and Q₄, the reduced levels of signals arenegligible due to the fact that these gate capacities are very small.Also, the difference in potential between the bit lines BL₁ and BL₁ isamplified by the transistors Q₃ and Q₄, so that the transmission ofsignals from the bit lines BL₁ and BL₁ to the read bus lines RB and RBis carried out at a high speed.

The N-channel transistors Q₅ and Q₆ of the amplifier AMP are interposedbetween the sources of the N-channel transistors Q₃ and Q₄ thereof andthe ground GND, and is controlled by a Y selection signal φ_(Y1R) for aread mode. Therefore, only during a read mode (φ_(Y1R) ="1"), thetransistors Q₅ and Q₆ are turned ON to activate the amplifier AMP.

Note that a Y selection signal φ_(Y1W) for a write operation is used forturning ON the transistors Q₁ and Q₂. Therefore, the read bus lines RBand RB and the write bus lines WB and WB are selectively operated for aread mode and a write mode.

Further, transistors Q₇ and Q₈ are interposed between the bit lines BL₁and BL₁ and the sense amplifier SA₁. The transistors Q₇ and Q₈ areturned ON and OFF by a clock signal φ_(TS). Therefore, during a readmode when the signals at the bit lines BL₁ and BL₁ are transmitted bythe amplifier AMP to the read bus lines RB and RB, the transistors Q₇and Q₈ are turned OFF by the clock signal φ_(TS) to separate the senseamplifier SA₁ from the bit lines BL₁ and BL₁ . As a result, since thecapacity of the sense amplifier SA₁ does not affect the operation of thebit lines BL₁ and BL₁ , the read operation speed can be enhanced. Then,after the operation of the read bus lines RB and RB has beensufficiently advanced, the transistors Q₇ and Q₈ are turned ON by theclock signal φ_(TS), to thereby activate the sense amplifier SA₁, thuscarrying out a refresh operation.

In FIG. 6, reference numeral 1 designates a control circuit forreceiving a read/write signal R/W, a row address strobe signal RAS and acolumn address strobe signal CAS, to generate the read signal φ_(R), theclock signal φ_(TS), the sense activation signal φ_(S), an X addresscontrol signal φ_(x), a Y address control signal φ_(YR) for a readoperation, and a Y address control signal φ_(YW). Also, an X addressbuffer/decoder 2 is triggered by the X address control signal φ_(x) toreceive X address signals ADDX, to select one of the word lines WL₁,WL₂, . . . and make it high (V_(cc) +α). Further, a Y addressbuffer/decoder 3 is triggered by the Y address control signal φ_(YR) orthe Y address control signal φ_(YW) to receive Y address signals ADDY,thus selecting one of the Y selection signals such as φ_(Y1R) or one ofthe Y selection signals such as φ_(Y1W) and make it high.

As illustrated in FIG. 7, the read amplifier RA' is constructed by anamplifier AMP₁ formed by P-channel transistors Q₉ and Q₁₀, N-channeltransistors Q₁₁, Q₁₂ and Q₁₃, and an amplifier AMP₂ formed by P-channeltransistors Q₁₄ and Q₁₅, N-channel transistors Q₁₆, Q₁₇ and Q₁₈. In theamplifier AMP₁, the transistors Q₉ and Q₁₀ form a current mirrorcircuit, and the transistors Q₁₁ and Q₁₂ form a current switch. Theamplifier AMP₁ is controlled by the read signal φ_(R) to amplify thedifference in potential between the read bus lines RB and RB, thusgenerating the read data signal D_(OUT). Similarly, in the amplifierAMP₂, the transistors Q₁₄ and Q₁₅ form a current mirror circuit, and thetransistors Q₁₆ and Q₁₇ form a current switch. The amplifier AMP₁ iscontrolled by the read signal φ_(R) to amplify the difference inpotential between the read bus lines RB and RB, thus generating the readdata signal D_(OUT).

Thus, in the first embodiment as illustrated in FIG. 6, since thesignals at the bit lines BL₁ and BL₁ are transmitted to the read buslines RB and RB before the operation of the sense amplifier SA₁, thelevels of signals transmitted from the memory cell C₁₁ to the bit linesBL₁ and BL₁ are as large as possible. The levels of signals aredependent upon the capacitance ratio of the bit lines to the memorycell, and the capacitance of the bit lines includes the capacitance ofthe sense amplifier SA₁ in the prior art. In the first embodiment,however, the capacitance of the bit lines contributing to a readoperation does not include the capacitance of the sense amplifier SA₁,since the sense amplifier SA₁ is separated from the bit lines BL₁ andBL₁ before the operation of the sense amplifier SA₁. Here, since thecapacitance of the sense amplifier SA₁ is about half of that of the bitlines BL₁ and BL₁ per se, the levels of signals at the bit lines BL₁ andB₁ before the operation of the sense amplifier SA₁ can about be 1.5times that in the prior art, to thereby contribute to the operation ofthe amplifier AMP.

Note that the sense amplifier SA₁ is not unnecessary, that is, the senseamplifier SA₁ carries out a refresh operation after the bit lines BL₁and BL₁ are connected to the sense amplifier SA₁.

A read operation upon the device of FIG. 6 is explained next withreference to FIG. 8. Assume that the bit lines BL₁ and BL₁ areprecharged at V_(cc) /2 and the read bus lines RB and RB are prechargedat V_(cc) by a precharging circuit (not shown).

At time t₀, an external row address strobe signal RAS is made low toenter a selection mode. As a result, the control circuit 1 is operatedto change the clock signal φ_(TS) from high (V_(cc) +α) to low (GND).Thus, the sense amplifier SA₁ is separated from the bit lines BL₁ andBL₁ . Also, the control circuit 1 generates the X address access signalφ_(x) and transmits it to the X address buffer/decoder 2.

Then, at time t₁, the X address buffer/decoder 1 selects one word linesuch as WL₁ and changes it from low (GND) to high (V_(cc) +α).

When the voltage at the word line WL₁ is made higher, the transistor ofthe memory cel C₁₁ is completely turned ON. As a result, the charge atthe node N₁₁ is divided between the the capacitor of the memory cell C₁₁and the bit line BL₁, and therefore, a difference ΔV in potential isgenerated between the bit lines BL₁ and BL₁ . In this case, thedifference ΔV in potential is larger than the prior art, since thecapacitance of the sense amplifier SA₁ does not contribute to thecapacitance of the bit lines BL₁ and BL₁ . As a result, the voltages atthe bit lines BL₁ and BL₁ are applied to the gates of the transistors Q₃and Q₄, respectively, of the amplifier AMP.

At time t₂, when the charge at the memory cell C₁₁ is completelydischarged to the bit line BL₁, the Y address buffer/decoder 3 istriggered by the clock signal φ_(YR) to receive the Y address signalsADDY, to select one of the Y selection signals, such as φ_(Y1R) andchange it from low (GND) to high. As a result, the transistors Q₅ and Q₆of the amplifier AMP are turned ON, so that the signals at the bit linesBL₁ and BL₁ are read out to the read bus lines RB and RB. Note that, inthis case, the voltages at the read bus lines RB and RB do not reachGND. Next, the control circuit 1 changes the read signal φ_(R) from low(GND) to high, to operate the read amplifier RA', and therefore, thesignals at the read bus lines RB and RB are transferred to the outputdata lines D_(OUT) and D_(OUT).

Next, at time t₃, the control circuit 1 changes the clock signal φ_(TS)from low (GND) to high (V_(cc) +α) to turn ON the transistors Q₇ and Q₈.Thus, the bit lines BL₁ and BL₁ are connected to the sense amplifierSA₁, to enter a refresh mode. After a little time has passed, thetransistors Q_(SP) and Q_(SN) of the sense amplifier SA₁ are turned ONby the sense activation signals φ_(S) and φ_(S), that is, the senseamplifier SA₁ is activated by causing the voltage lines φ_(SP) andφ_(SN) to be V_(cc) and 0 V (GND), respectively. As a result, thevoltage at the bit line BL₁ on a lower voltage side becomes 0 V, and thevoltage at the bit line BL₁ becomes V_(cc), thus carrying out a senseoperation as well as a refresh operation.

Then, at time t₄, the control returns to a stand-by mode.

As shown in FIG. 4, in the prior art, the control enters a read modeafter entering a refresh mode. Conversely, as shown in FIG. 8, in thefirst embodiment, the control enters a read mode before entering arefresh mode.

In FIG. 9, which illustrates a second embodiment of the presentinvention, the bit lines are divided into two portions, to therebyincrease the levels of signals transmitted from the memory cells to thebit lines. That is, since the bit lines are divided at their centerportions, the read bus lines RB and RB and the amplifier RA' areconnected to the center portions. Also, a control circuit 4 is added.The control circuit 4 receives the clock signal φ_(TS) and one X addresssignal such as AX₀ to generate two clock signals φ_(TU) and φ_(TL) whichare supplied to a pair of transistors Q₁₉ and Q₂₀ and a pair oftransistors Q₂₁ and Q₂₂.

A read operation of the device of FIG. 9 is explained next withreference to FIG. 10. In FIG. 10, the operation ofconnection/disconnection of the bit lines is mainly shown, and thevoltages of the bit lines, which are the same as those of FIG. 6, areomitted.

In a stand-by state before time t₀, all of the clock signals φ_(TS),φ_(TU) and φ_(TL) are high (V_(cc) +α), and therefore, all of thetransistors Q₇, Q₈, Q₁₉, Q₂₀, Q₂₁ and Q₂₂ are turned ON. Also, the bitlines BL₁ and BL₁ are precharged at V_(cc) /2 by the precharging circuit(not shown).

At time t₀, the row address strobe signal RAS is made low to enter aselection mode. As a result, at time t₁, the control circuit 1 isoperated to change the clock signal φ_(TS) from high (V_(cc) +α) to low(GND). Thus, the sense amplifier SA₁ is separated from the bit lines BL₁and BL₁ .

At time t₂, the control circuit 4 changes one of the clock signalsφ_(TU) and φ_(TL) from high (V_(cc) +α) to low (GND) in accordance withthe one bit AX₀ of the X address signals ADDX. That is, the portion ofthe bit lines, to which a selected memory cell is connected, isseparated from the amplifier AMP. For example, when the word line WL₁ isselected, the clock signal φ_(TL) is made low to turn OFF thetransistors Q₂₁ and Q₂₂. Conversely, when the word line WL₁ ' isselected, the clock signal φ_(TU) is made low to turn OFF thetransistors Q₁₉ and Q₂₀.

Next, at time t₃, one word line such as WL₁ is changed from low (GND) tohigh (V_(cc) +α), the signal of the memory cell C₁₁ is generated in thebit line BL₁.

Next, at time t₄, the Y selection signal φ_(Y1R) for a read operation ischanged from low (GND) to high (V_(cc) +α), so that the signals at thebit lines BL₁ and BL₁ are transferred to the read bus lines RB and RB.

At time t₅, the read signal φ_(R) is changed from low (GND) to high(V_(cc) +α), so that the difference in potential between the read buslines RB and RB is amplified by the read amplifier RA'. Thus, the readdata signals D_(OUT) and D_(OUT) are generated from the read amplifierRA'.

At time t₆, when the read operation by the read amplifier RA' has beenproceeded, the clock signals φ_(TS), φ_(TU) and φ_(TL) are all made high(V_(cc) +α). As a result, the bit lines BL₁ and BL₁ are connected to thesense amplifier SA₁.

Next, at time t₇, the sense activation signal φ_(s) is changed from low(GND) to high (V_(cc) +α), to activate the sense amplifier SA₁, enteringa refresh mode.

Finally, at time t₈, the row address strobe signal RAS is changed fromlow to high, so that the control returns to a stand-by mode.

Thus, in the second embodiment, the capacitance of a portion of the bitlines contributing to a read operation does not include half of that ofthe bit lines per se including the capacitance of the sense amplifierSA₁, since the half of the bit lines as well as the sense amplifier SA₁are separated from the portion of the bit lines BL₁ and BL₁ , to whichthe selected word line such as WL₁ is connected, before the senseamplifier SA₁ is operated. That is, the capacitance contributed to theread operation is about 1/3 as compared with the prior art, andtherefore, the levels of signals at the bit lines BL₁ and BL₁ before theoperation of the sense amplifier SA₁ can be about 3 times that of theprior art, to thereby contribute to the operation of the amplifier AMP.

In FIG. 11, which illustrates a third embodiment of the presentinvention, the memory cells are divided into 2N (N=2, 3, . . .) memorycell arrays MCA₁, MCA₂, . . . , and MCA_(2N). In FIG. 11, a row ofamplifiers AMP and a read amplifier such as RA₁ ' are provided for everytwo memory cell arrays. Also, transistors controlled by clock signalsφ_(T1), φ_(T2), . . . are provided between the memory cell arrays suchas MCA₂ and MCA₃ and between the memory cell array such as MCA₁ and therow of amplifiers AMP.

Thus, in the third embodiment, the capacitance of the bit lines of oneselected memory cell array contributing to a read operation does notincludes that of the bit lines of the other non-selected memory cellarrays including the capacitance of the sense amplifier SA₁, since thebit lines of the other memory cell arrays as well as the sense amplifierSA₁ are separated from the bit lines BL₁ and BL₁ of the selected memorycell array connected, before the sense amplifier SA₁ is operated. Thatis, the capacitance contributed to the read operation is remarkablyreduced as compared with the prior art, and therefore, the levels ofsignals at the bit lines BL₁ and BL₁ before the operation of the senseamplifier SA₁ can be remarkably increased as compared with the priorart, to thereby contribute to the operation of the amplifier AMP.

As explained hereinbefore, according to the present invention, sincesignals at bit lines are transferred to read bus lines special for aread operation before the operation of sense amplifiers, a readoperation speed can be enhanced.

I claim:
 1. A dynamic semiconductor memory device comprising:a pluralityof word lines; a plurality of bit lines; a plurality of dynamic memorycells, each connected between one of said word lines and one of said bitlines; a plurality of sense amplifiers, each connected to one pair ofsaid bit lines; a plurality of switching circuits, each connectedbetween one pair of said bit lines and one of said sense amplifier; tworead bus lines; a plurality of switching amplifiers, each connectedbetween one pair of said bit lines and said read bus lines; and acontrol means, connected to said sense amplifiers, said switchingcircuits and said switching amplifiers, for turning ON one of saidswitching amplifiers to carry out a read operation, and thereafter,turning ON said switching circuits to carry out a refresh operation. 2.A device as set forth in claim 1, wherein said control means activatessense amplifiers after said switching circuits are turned ON.
 3. Adevice as forth in claim 1, further comprising a read amplifier,connected to said read bus lines, for amplifying voltages at said readbus lines.
 4. A device as set forth in claim 1, wherein each of saidswitching amplifiers comprises:first and second transistors, each havinga drain connected to one of said read bus lines and a gate connected toone of said bit lines; and third and fourth transistors each having adrain connected to a source of one of said first and second transistors,a gate controlled by said control means and a source connected to adefinite voltage source.
 5. A dynamic semiconductor memory devicecomprising:a plurality of word lines; a plurality of bit lines; aplurality of dynamic memory cells, each connected between one of saidword lines and one of said bit lines; a plurality of sense amplifiers,each connected to one pair of said bit lines; a plurality of switchingcircuits, each connected between one pair of said bit lines and one ofsaid sense amplifier; two read bus lines; a plurality of switchingamplifiers, each connected capacitively between one pair of said bitlines and said read bus lines; a read amplifier connected to said readbus lines; and a control means, connected to said word lines, said senseamplifiers, said switching circuit, said switching amplifiers and saidread amplifier, for selecting one of said word lines to enter aselection mode, thereafter operating one of said switching amplifiersand said read amplifier to enter a read mode, and thereafter operatingone of said switching circuits and said sense amplifiers to enter arefresh mode.
 6. A device as set forth in claim 5, wherein each of saidswitching amplifiers comprises:first and second transistors, each havinga drain connected to one of said read bus lines and a gate connected toone of said bit lines; and third and fourth transistors each having adrain connected to a source of one of said first and second transistors,a gate controlled by said control means and a source connected to adefinite voltage source.
 7. A dynamic semiconductor memory devicecomprising:a first group of word lines; a second group of word lines; aplurality of bit lines; a plurality of dynamic memory cells, eachconnected between one of said word lines and one of said bit lines; aplurality of sense amplifiers, each connected to one pair of said bitlines; a plurality of first switching circuits, each connected betweenone pair of said bit lines and one of said sense amplifier; two read buslines; a plurality of switching amplifiers, each connected between onepair of said bit lines and said read bus lines; a plurality of secondswitching circuits, each provided between said first group of word linesand one of said switching amplifiers, for connecting a portion of saidbit lines on the side of said first group of word lines to the one ofsaid switching amplifiers; a plurality of third switching circuits, eachprovided between said second group of word lines and one of saidswitching amplifiers, for connecting a portion of said bit lines on theside of said second group of word lines to the one of said switchingamplifiers; a control means, connected to said sense amplifiers, saidfirst, second and third switching circuits and said switchingamplifiers, for turning ON one of said second and third switchingcircuits and one of said switching amplifiers to carry out a readoperation, and thereafter, turning ON said first switching circuits andthe other of said second and third switching circuits to carry out arefresh operation.
 8. A device as set forth in claim 7, wherein saidcontrol means activates sense amplifiers after said first switchingcircuits is turned ON.
 9. A device as forth in claim 7, furthercomprising a read amplifier, connected to said read bus lines, foramplifying voltages at said read bus lines.
 10. A device as set forth inclaim 7, wherein each of said switching amplifiers comprises:first andsecond transistors, each having a drain connected to one of said readbus lines and a gate connected to one of said bit lines; and third andfourth transistors each having a drain connected to a source of one ofsaid first and second transistors, a gate controlled by said controlmeans and a source connected to a definite voltage source.
 11. A dynamicsemiconductor memory device comprising:a first group of word lines; asecond group of word lines; a plurality of bit lines; a plurality ofdynamic memory cells, each connected between one of said word lines andone of said bit lines; a plurality of sense amplifiers, each connectedto one pair of said bit lines; a plurality of first switching circuits,each connected between one pair of said bit lines and one of said senseamplifier; two read bus lines; a plurality of switching amplifiers, eachconnected capacitively between one pair of said bit lines and said readbus lines; a plurality of second switching circuits, each providedbetween said first group of word lines and one of said switchingamplifiers, for connecting a portion of said bit lines on the side ofsaid first group of word lines to the one of said switching amplifiers;a plurality of third switching circuits, each provided between saidsecond group of word lines and one of said switching amplifiers, forconnecting a portion of said bit lines on the side of said second groupof word lines to the one of said switching amplifiers; a read amplifierconnected to said read bus lines; and a control means, connected to saidsense amplifiers, said first, second and third switching circuits, saidswitching amplifiers and said read amplifier, for turning ON one of saidsecond switching circuits said third switching circuits and selectingone of said word lines to enter a selection mode, thereafter, operatingone of said switching amplifiers and said read amplifier to enter a readmode, and thereafter turning ON said first switching circuits and theother of said second and third switching circuits and operating saidsense amplifiers to enter a refresh mode.
 12. A device as set forth inclaim 11, wherein each of said switching amplifiers comprises:first andsecond transistors, each having a drain connected to one of said readbus lines and a gate connected to one of said bit lines; and third andfourth transistors each having a drain connected to a source of one ofsaid first and second transistors, a gate controlled by said controlmeans and a source connected to a definite voltage source.
 13. A dynamicsemiconductor memory device comprising:a plurality of groups of wordlines; a plurality of bit lines; a plurality of dynamic memory cells,each connected between one of said word lines and one of said bit lines;a plurality of sense amplifiers, each connected to one pair of said bitlines; a plurality of first switching circuits, each connected betweenone pair of said bit lines and one of said sense amplifier; a pluralityof pairs of read bus lines, each pair being provided for every twogroups of said word lines; a plurality of groups of switchingamplifiers, each group connected between one pair of one group of saidbit lines and said read bus lines; a plurality of groups of secondswitching circuits, each group provided between one group of said wordlines and one group of said switching amplifiers, for connecting aportion of said bit lines on the side of the one group of said wordlines to the one group of said switching amplifiers; and a controlmeans, connected to said sense amplifiers, said first and secondswitching circuits and said switching amplifiers, for turning ON onegroup of said second switching circuits and one group of said switchingamplifiers to carry out a read operation, and thereafter, turning ONsaid first switching circuits and the other group of said secondswitching circuits to carry out a refresh operation.
 14. A device as setforth in claim 13, wherein said control means activates sense amplifiersafter said first switching circuits is turned ON.
 15. A device as forthin claim 13, further comprising a plurality of read amplifiers, eachconnected to one pair of said read bus lines, for amplifying voltages atthe pair of said read bus lines.
 16. A device as set forth in claim 13,wherein each of said switching amplifiers comprises:first and secondtransistors, each having a drain connected to one of said read bus linesand a gate connected to one of said bit lines; and third and fourthtransistors each having a drain connected to a source of one of saidfirst and second transistors, a gate controlled by said control meansand a source connected to a definite voltage source.
 17. A dynamicsemiconductor memory device comprising:a plurality of groups of wordlines; a plurality of bit lines; a plurality of dynamic memory cells,each connected between one of said word lines and one of said bit lines;a plurality of sense amplifiers, each connected to one pair of said bitlines; a plurality of first switching circuits, each connected betweenone pair of said bit lines and one of said sense amplifier; a pluralityof pairs of read bus lines, each pair being provided for every twogroups of said word lines; a plurality of groups of switchingamplifiers, each group connected capacitively between one pair of onegroup of said bit lines and said read bus lines; a plurality of groupsof second switching circuits, each group provided between one group ofsaid word lines and one group of said switching amplifiers, forconnecting a portion of said bit lines on the side of the one group ofsaid word lines to the one group of said switching amplifiers; aplurality of read amplifiers, each connected to one group of said readbus lines; and a control means, connected to said sense amplifiers, saidfirst and second switching circuits, said switching amplifiers and saidread amplifiers, for turning ON one group of said second switchingcircuits and selecting one group of said word lines to enter a selectionmode, thereafter, operating one group of said switching amplifiers andone of said read amplifiers to enter a read mode, and thereafter turningON said first switching circuits and the other groups of said secondswitching circuits and operating said sense amplifiers to enter arefresh mode.
 18. A device as set forth in claim 17, wherein each ofsaid switching amplifiers comprises:first and second transistors, eachhaving a drain connected to one of said read bus lines and a gateconnected to one of said bit lines; and third and fourth transistorseach having a drain connected to a source of one of said first andsecond transistors, a gate controlled by said control means and a sourceconnected to a definite voltage source.